Compact system module with built-in thermoelectric cooling

ABSTRACT

An improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.

This application is a divisional of U.S. application Ser. No. 10/606,539filed Jun. 26, 2003, which is a divisional of U.S. application Ser. No.09/144,307 filed on Aug. 31, 1998, now U.S. Pat. No. 6,586,835, whichare incorporated herein by reference.

1. Field of the Invention

The present invention relates generally to semiconductor integratedcircuits. More particularly, it pertains to a compact system module withbuilt-in thermoelectric cooling.

2. Background of the Invention

Integrated circuit technology relies on transistors to formulate vastarrays of functional circuits. The complexity of these circuits requiresthe use of an ever increasing number of linked transistors. As thenumber of transistors required increases, the integrated circuitrydimensions shrink. It is one objective in the semiconductor industry toconstruct transistors and other discrete devices which occupy lesssurface area on a given silicon chip/die. At the same time, thesemiconductor industry seeks to increase the speed and power offered byintegrated circuits. One approach to the latter challenge is through thedevelopment of improved methods for electrically connecting andpackaging circuit devices which are fabricated on the same or ondifferent silicon chips.

Ideally, we would like to build a computing system by fabricating allthe necessary integrated circuits on one wafer or chip, as compared withtoday's method of fabricating many chips of different functions andpackaging them to assemble a system. A true “system on a chip” wouldgreatly improve integrated circuit performance and provide higherbandwidth. Unfortunately, it is very difficult with today's technologyto implement a truly high-performance “system on a chip” because ofvastly different fabrication processes and different manufacturingyields for the logic and memory circuits.

As a compromise, various “system modules” have been introduced thatelectrically connect and package circuit devices which are fabricated onthe same or on different semiconductor chips. These began with simplystacking two semiconductor chips, e.g. a logic and memory chip, one ontop of the other in an arrangement commonly referred to as chip-on-chip(COC) structure. Chip-on-chip structure most commonly utilizes microbump bonding technology (MBB) to electrically connect the two chips.Several problems, however, remain inherent with this design structure.One serious complication includes the heating which occurs mostseriously in connection with a logic chip such as a microprocessor. Inhigh-performance microprocessors, where CPUs are running at 500 MHz anddissipating up to 85 watts of power, cooling becomes a crucial issue.

Usually, the cooling of such a package is accomplished by forced air. Incertain applications, however, forced air cooling is not feasible orpractical. Examples of such applications include computers to be used inouter space, in a vacuum environment on earth, or in clean rooms whereair circulation is not desirable. For these and other instances, adifferent method of cooling is required. Another cooling method includesliquid cooling, such as the forced water cooling used in the thermalconduction modules of 113M main frame computers and forced freon coolingused in Cray supercomputers. Still, liquid cooling methods can alsoprove too bulky, costly, and not easily adapted for use in compacthigh-performance integrated circuit systems, e.g. portable devices.

Thus, it is desirable to develop an improved structure and method forcooling high performance integrated circuit systems. Additionally, theimproved structure and method should accommodate a dense integration andpackaging for semiconductor chips, e.g. logic and memory chips.

SUMMARY OF THE INVENTION

The above mentioned problems with integrated circuits and other problemsare addressed by the present invention and will be understood by readingand studying the following specification. An integrated circuit packagewhich accords improved performance is provided.

In particular, an improved integrated circuit package for providingbuilt-in heating or cooling to a semiconductor chip is provided. Theimproved integrated circuit package provides increased operationalbandwidth between different circuit devices, e.g. logic and memorychips. The improved integrated circuit package does not require changesin current CMOS processing techniques. The structure includes the use ofa silicon interposer. The silicon interposer can consist of recycledrejected wafers-from the front-end semiconductor processing.Micro-machined vias are formed through the silicon interposer. Themicro-machined vias include electrical contacts which couple variousintegrated circuit devices located on the opposing surfaces of thesilicon interposer. The packaging includes a Peltier element.

The Peltier element, using semiconductor-based materials, functions as asmall heat pump. By applying a low-voltage d-c current to the Peltierelement thermal energy is transferred with the effect that one portionof the Peltier element is cooled and another heated. In one embodiment,the heated portion of the Peltier element is in contact with a heat sinkor the outer cover of the integrated circuit package and the cooledportion is in contact with a semiconductor chip. Thus providing improvedcooling for high frequency, high speed microprocessor chip components.In an alternative embodiment, the arrangement is reversed. This designhas no moving parts, is small in size and lightweight, and has theability to cool below or heat above the ambient temperature surroundingintegrated circuit devices.

These and other embodiments, aspects, advantages, and features of thepresent invention will be set forth in part in the description whichfollows, and in part will become apparent to those skilled in the art byreference to the following description of the invention and referenceddrawings or by practice of the invention. The aspects, advantages, andfeatures of the invention are realized and attained by means of theinstrumentalities, procedures, and combinations particularly pointed outin the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional view illustrating an electronic packagingassembly according to the teachings of the present invention.

FIG. 1B is a cross-sectional view illustrating in greater detail aportion of a particular embodiment for the present invention.

FIG. 2 is a cross-sectional view illustrating an embodiment of a Peltierelement according to the teachings of the present invention.

FIG. 3 is a block diagram illustrating an electronic system according toan embodiment of the present invention.

FIGS. 4A-4G illustrate an embodiment of a process of fabrication for aportion of an embodiment of the present invention.

FIG. 5 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention.

FIG. 6 illustrates, in flow diagram form, a methodical aspect forforming an electronic packaging assembly according to the teachings ofthe present invention.

FIG. 7 illustrates, in flow diagram form, a methodical aspect forpackaging an integrated circuit according to the teachings of thepresent invention.

FIG. 8 illustrates, in flow diagram form, an embodiment for the methodof cooling an integrated circuit according to the teachings of thepresent invention.

FIG. 9 illustrates, in flow diagram form, an embodiment for the methodof heating an integrated circuit according to the teachings of thepresent invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention.

The terms wafer and substrate used in the following description includeany structure having an exposed surface with which to form theintegrated circuit (IC) structure of the invention. The term substrateis understood to include semiconductor wafers. The term substrate isalso used to refer to semiconductor structures during processing, andmay include other layers that have been fabricated thereupon. Both waferand substrate include doped and undoped semiconductors, epitaxialsemiconductor layers supported by a base semiconductor or insulator, aswell as other semiconductor structures well known to one skilled in theart. The term conductor is understood to include semiconductors, and theterm insulator is defined to include any material that is lesselectrically conductive than the materials referred to as conductors.The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

The term “horizontal” as used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizonal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate.

Throughout this specification the designation “n+” refers tosemiconductor material that is heavily doped n-type semiconductormaterial, e.g., monocrystalline silicon or polycrystalline silicon.Similarly, the designation “p+” refers to semiconductor material that isheavily doped p-type semiconductor material. The designations “n−” and“p−” refer to lightly doped n and p-type semiconductor materials,respectively.

Several illustrative embodiments of the present invention are providedbelow. In one illustrative embodiment of the present invention includesan electronic packaging assembly. The electronic packaging assemblyincludes a silicon interposer which has a first and second, or opposingsides. At least one semiconductor chip is provided on a first side ofthe silicon interposer. The semiconductor chip on the first side of thesilicon interposer is coupled to a metal-to-semiconductor junction. Atleast one semiconductor chip is similarly provided on a second side ofthe silicon interposer. A number of electrical connections are formedthrough the silicon interposer and couple the semiconductor chipslocated on each side of the silicon interposer.

In another embodiment, an electronic system module is provided theelectronic system module includes a silicon interposer having opposingsurfaces. A microprocessor, which has a circuit side, faces a first oneof the opposing surfaces of the silicon interposer. The microprocessoron the first side of the silicon interposer is coupled to ametal-to-semiconductor junction. A memory chip, which has a circuitside, faces a second one of the opposing surfaces of the siliconinterposer. A number of electrical connections extend through thesilicon interposer and couple the circuit side of the microprocessor tothe circuit side of the memory chip.

In another embodiment, a computer system is provided. The computersystem includes an electronic packaging assembly as presented anddescribed above. A number of external devices are connected to theelectronic packaging assembly by a system bus.

In another embodiment of the present invention, a method for cooling anintegrated circuit is provided. The method includes using, or providing,a silicon interposer with opposing sides and coupling a firstsemiconductor chip to a first side and coupling a second semiconductorchip to a second side of the silicon interposer. A number of electricalconnections through the silicon interposer electrically connect thefirst semiconductor chip to the second semiconductor. The method furtherincludes forming a metal-to-semiconductor junction connected to thefirst semiconductor chip. A current is then passed through themetal-to-semiconductor junction in a direction so as to draw thermalenergy away from the first semiconductor chip.

In another embodiment of the present invention, a method for heating anintegrated circuit is provided. The method includes using, or providing,a silicon interposer with opposing sides and coupling a firstsemiconductor chip to a first side and coupling a second semiconductorchip to a second side of the silicon interposer. A number of electricalconnections through the silicon interposer electrically connect thefirst semiconductor chip to the second semiconductor. The method furtherincludes forming a metal-to-semiconductor junction connected to thefirst semiconductor chip. A current is then passed through themetal-to-semiconductor junction in a direction so as to draw thermalenergy to the first semiconductor chip.

FIG. 1A is a cross-sectional view illustrating an electronic packagingassembly 100, or electronic system module 100, according to theteachings of the present invention. FIG. 1A includes a siliconinterposer 110. The silicon interposer 110 has opposing surfaces whichinclude a first one 115 of the opposing surfaces, or first side 115 anda second one 120 of opposing surfaces, or second side 120. In oneexemplary embodiment, the silicon interposer 110 includes rejectedsilicon wafers which have been recycled from the front-end of thesemiconductor fabrication process. The silicon interposer 110 may haveactive and passive devices built on one or both sides, 115 and 120.Further, the active and passive devices built on one or both sides, 115and 120, can also include simple capacitors using the insulator andmetallurgy on one side of the interposer, and can include devices suchas, for example driver circuits. The electronic packaging assembly 100includes a number of flip chips, 125A, 125B, . . . , 125N respectively,located on the first side 115 of the silicon interposer 110. Theelectronic packaging assembly 100 additionally includes a number of flipchips, 125AA, 125BB, . . . , 125NN respectively, located on the secondside 120 of the silicon interposer 110. In one embodiment, the a numberof flip chips, 125A, 125B, . . . , 125N respectively, located on thefirst side 115 includes at least one semiconductor chip which is amicroprocessor chip or other suitable logic chip. In one embodiment, thenumber of flip chips, 125AA, 125BB, . . . , 125NN respectively, locatedon the second side 120 includes at least one semiconductor chip which isa memory chip. The memory chip can include a dynamic random accessmemory (DRAM)-type chip. Likewise, the memory chip can include a staticrandom access memory (SRAM)-type chip or flash electrically erasableprogram read only memory (flash EEPROM)-type chip.

In alternative embodiments, the nature of the flip, or semiconductor,chips coupled to the first and second sides, 115 and 120 respectively,can be reversed or varied in any desired order. In one embodiment,capacitors are similarly included amongst the number of flip-chips,125A, 125B, . . . , 125N, or, 125AA, 125BB, . . . 125NN, and coupled tothe first or second side, 115 and 120 respectively. Likewise,microprocessors and memory chips may be coupled to the same side of thesilicon interposer. In one embodiment, a second or even multiplemicroprocessors, capacitors, and memory chips are included in the numberof flip-chips, 125A, 125B, . . . , 125N, or, 125AA, 125BB, . . . ,125NN, and are coupled with their circuit side 130 facing the first orsecond side, 115 and 120 respectively, of the silicon interposer 110.

In constructing the silicon interposer 110 it is of course necessary tocomplete all the high-temperature process steps prior to the depositionof the interconnection metallurgy. In one embodiment, themicroprocessors or logic chips are included amongst the number offlip-chips, 125A, 125B, . . . , 125N, and are mounted with the circuitside 130 face-down (active circuit facing downward) to the siliconinterposer 110 by a ball-grid array (BGA) 131, micro-bump bonding (MBB)131, or controlled collapse chip connections (C-4) 131. In the sameembodiment, DRAM chips which are included amongst the number offlip-chips, 125AA, 125BB, . . . , 125NN and are mounted on the otherside of the silicon interposer 110 with the circuit side 130 facingupward using the same or similar connection technology. Since chips willbe mounted on both sides of the interposer one must be cognizant of theeffects of high temperature on the solder joints previously made. Thisproblem may be solved either by using only localized heating to reflowthe solder on the second surface 120 or by using an appropriate solderhierarchy. In one embodiment, lead 2.5% (by weight) Pb—Sn solder is usedon the C-4 joints of the chips, 125A, 125B, . . . , 125N, mounted on thefirst side 115. In the same embodiment then, Pb-11 wt. % Sb is used forthe chips, 125AA, 125BB, . . . , 125NN, mounted on the second side 120,and Pb-62 Wt % Sn is used for card soldering. In alternativeembodiments, other lower-melting point alloys, for example, Ga-basedalloys can also be used.

FIG. 1A further illustrates that a number of electrical connections 135couple the number of semiconductor chips, 125A, 125B, . . . , 125N,mounted on the first side 115 to the number of semiconductor chips,125AA, 125BB, . . . , 125NN, mounted on the second side 120 of thesilicon interposer 110. The number of electrical connections 135 includemicro-machined vias which are formed according to the detaileddescription provided below in connection with FIGS. 4A-4G. The detaileddescription below for the number of electrical connections 135 isprovided according to techniques taught in co-pending application Ser.No. 08/917,443, entitled “Integrated Circuitry and Methods of FormingIntegrated Circuitry,” filed on Aug. 22, 1997 or according to techniquestaught in application Ser. No. 08/917,449, entitled “Methods of FormingCoaxial Integrated Circuitry Interconnect Lines, and IntegratedCircuitry,” filed on Aug. 22, 1997, which applications are incorporatedherein by reference.

In one embodiment, as illustrate by FIG. 1A, at least one of the numberof semiconductor chips, 125A, 125B, . . . , 125N, is further coupled toa metal-to-semiconductor junction 160, or any other suitable PeltierJunction 160 which will produce a Peltier effect. In this application, acurrent passed through a Peltier Junction 160 is defined to produce aPeltier effect.

The Peltier effect is essentially the reverse of a thermocouple effect.When a current is passed through a circuit formed from two dissimilarmetals or from a metal and a semiconductor, or even certain other alloysand compounds, one junction gives off heat and is cooled and the otherabsorbs heat and becomes warm. The effect is reversible, e.g., if thecurrent is reversed, thermal energy will be drawn in the oppositedirection, the cool junction becomes warm and the hot junction cools.Larger temperature differences are produced with metal-to-semiconductorjunctions than with metal-to-metal junctions. A metal-n-type junctionproduces a temperature difference in the opposite sense to that of ametal-p-type junction for the same direction of current flow. A numberof such junctions can be used to form a Peltier element, an example ofwhich is shown in FIG. 2.

The amount of thermal energy transferred, for a given current, dependson the conductors. The thermal energy that is emitted or absorbed withthe passage of current through a junction of dissimilar conductors iscalled the Peltier heat. The quotient of the Peltier heat and thecurrent is called the Peltier coefficient. Also, a coefficient ofperformance (COP) is defined in terms of the ratio of the quantity ofabsorbed heat to the inputted power.

FIG. 1B is a cross-sectional view illustrating in greater detail aportion of an exemplary embodiment of the present invention. In FIG. 1B,Peltier element 160 includes a semiconductor material layer 128sandwiched between a first metal layer 127 and a second metal layer 129.The arrangement forms a first metal-to-semiconductor junction 171between the first metal layer 127 and the semiconductor material layer128. A second metal-to-semiconductor junction 174 is formed between thesecond metal layer 129 and the semiconductor material 128. In thisembodiment the semiconductor material can include a range ofsemiconductor materials. In one such embodiment, the semiconductormaterial layer 128 includes an alloy of Bismuth Telluride (Bi₂Te₃) thathas been suitably doped to provide either distinct “n” or “p”characteristics. Alternatively an alloy of Bismuth Telluride (Bi₂Te₃)can be suitably doped and organized to provide individual blocks ofelements having distinct “n” and “p” characteristics, as illustrated byn-type blocks, 202A, 202B, . . . , 202C, etc. and by p-type blocks,203A, 203B, . . . , 203C, etc. in FIG. 2.

Often, Bi₂Te₃ is used as the doped semiconductor material fornear-room-temperature applications. Lead Telluride (PbTe) and SiliconGermanium (SiGe) are frequently used as the doped semiconductor materialin higher temperature applications. Similarly suited doping techniquesare employed to create the individual layers, or blocks, of LeadTelluride (PbTe) and Silicon Germanium (SiGe) compounds having distinct“n” and “p” characteristics.

FIG. 1B illustrates one embodiment in which the silicon interposer 110is further connected to an integrated circuit package 136, or chippackage 136. One of ordinary skill in the art of semiconductorfabrication will understand the manner by which the silicon interposer110 may be connected to the chip package 136. An exemplary embodimentfor constructing the same is provided in U.S. Pat. No. 5,598,031, G.L.Groover, et al, “Electrically and thermally enhanced package using aseparate silicon substrate.” Another exemplary embodiment forconstructing the same is provided in U.S. Pat. No. 5,061,987, Hsia,Yukun, “Silicon substrate multichip assembly.” In the embodiment of FIG.1B, the chip package 136 has first and second electrical leads, 137 and138 respectively. Further, FIG. 1B illustrates that the electronicpackaging assembly 100 includes electrical coupling 139 between thefirst electrical lead 137 and the silicon interposer 110, and hence thesemiconductor chip 125. FIG. 1B, further illustrates an electricalcoupling 133 between the semiconductor chip 125 and the first metallayer 127. Also electrical coupling 139 is provided between the secondmetal layer 129 and a second electrical lead 138 on chip package 136. Inone embodiment, the electrical coupling, 139, 133, and 131 respectively,includes wire bonding. In an alternative embodiment, the electricalcoupling, 139, 133, and 131 respectively, includes any suitable couplingsuch as, for example, tape automated bonding (TAB).

FIG. 1A, illustrated an alternative chip package embodiment fortransmitting and receiving signals from the silicon interposer 110. InFIG. 1A, signal connections from the electronic packaging assembly 100to other components in an extended electronic system is provided byenergy-efficient optical fiber interconnections. The Peltier Junction160 included in FIG. 1A includes the “sandwich type” configurationillustrated by FIG. 1B, or an alternatively suited configuration suchas, for example, the embodiment illustrated by FIG. 2. The PeltierJunction 160 is coupled to at least one of the number of semiconductorchips, 125A, 125B, . . . , 125N, 125AA, 125BB, . . . , 125NN, found onthe silicon interposer 110. In the embodiment of FIG. 1A, the Peltierjunction 160 is shown coupled to chip 125A. The Peltier Junction 160functions according to operating techniques taught in this applicationor according to equivalents of the same.

FIG. 1A illustrates an optical receiver 140 adapted to receiving inputsignals from a fiber optical network 165. The optical receiver 140 isfurther coupled to a sense amplifier 145. The sense amplifier 145 andoptical receiver 140 are located on the silicon interposer 110. Thesense amplifier 145 is further coupled to at least one of the multiplesemiconductor chips, 125A, 125B, . . . , 125N, mounted on the first side115 of the silicon interposer 110. Also illustrated in FIG. 1A is anoptical emitter 150. The optical emitter 150 couples signals from atleast one of the multiple semiconductor chips, 125A, 125B, . . . , 125N,mounted on the first side 115 of the silicon interposer 110 to the fiberoptical network. FIG. 1A provides an illustration of the V-grooves 155located on the silicon interposer 110. Optical fibers 156 are mounted inthe V-grooves 155 on the silicon interposer 110. In one embodiment, theoptical receiver 140 includes a thyristor detector 140. Further, in oneparticular embodiment, the thyristor detector 140 includes a siliconthyristor detector 140. In an alternative embodiment, the thyristordetector 140 includes a gallium arsenide (GaAs) thyristor detector 140.In one embodiment, the optical emitter 150 includes a light-emittingdiode (LED) 150. The light-emitting diode (LED) 150 can be, forinstance, a gallium arsenide (GaAs) emitter. In one embodiment, thesense amplifier 145 includes a current sense amplifier 145. In oneembodiment, as illustrated in FIG. 1A, the coupling between the opticalemitter 150 and the fiber optical network 165 includes optical fibers156 mounted in V-grooves 155 on the silicon interposer 110. This opticalcoupling can be achieved in any suitable manner and can include two (2)way channel individual optical fibers 156. One exemplary embodiment forsuch optical coupling is provided by the method described in V.Vusirikala, et al., “Flip-chip optical fiber attachment to a monolithicoptical receiver chip,” Proc. SPIE Emerging Components and Technologiesfor all Optical Networks, Philadelphia, Pa. USA, 24 Oct. 1995, pp.52-58. In one embodiment, the optical emitter 150 is flip chip bonded tothe silicon interposer and an end 157 in a V-groove 155 is adapted toreflect light from the optical emitter 150 into the optical fibers 156.This technique, too can be achieved in any suitable manner such as, forexample, the method described in O. Vendier et al., “A 155 Mbps digitaltransmitter using GaAs thin film LEDs bonded to silicon drivercircuits,” Dig. IEEE/LEOS Summer Topical Mtg., Keystone Colo., 5-9 Aug.1996, pp. 15-16.

As stated previously the direction of the current flow through thePeltier junction 160 will determine the direction in which heat energyis transported. The following provides several exemplary embodiments ofoperation with reference to FIG. 1B. In one operational embodiment ofFIG. 1B, the semiconductor material includes a p-type semiconductormaterial 128. In this embodiment, a positive lead of a voltage supply isprovided to electrical lead 137 and a negative lead of a voltage supplyis provided to electrical lead 138. Thus, current is passed frompositive lead 137 in the direction of the arrow 170 across ametal-p-type semiconductor junction 171 located between the first metallayer 127 and p-type semiconductor material 128. According to thePeltier effect, thermal energy is thus drawn in, or follows, thedirection of the current flow through the p-type semiconductor. Thus, inthis operational embodiment of FIG. 1B, heat is drawn away from firstmetal layer 127 with a resultant cooling effect at junction 171 and aheating effect at junction 174. In this embodiment, thermal energy, orPeltier heat, is drawn away from chip 125A and the chip 125A is cooled.

Conversely, if the layer 128 remains p-type but the current flow isreversed, e.g., the polarity of the voltage supply is reversed, thenthermal energy continues to be drawn in, or follow, the direction ofcurrent flow, but the direction is now in the direction of arrow 172. Inthis operational embodiment of FIG. 1B, heat is drawn toward first metallayer 127 with a resultant heating effect at junction 171 and a coolingeffect at junction 174. In this embodiment, thermal energy, or Peltierheat is drawn toward chip 125A and chip 125A is heated.

In another exemplary embodiment of FIG. 1B, semiconductor layer 128 isan n-type semiconductor material 128. The positive lead of a voltagesupply is provided to electrical lead 137 and a negative lead of avoltage supply is provided to electrical lead 138. Current is passedfrom positive lead 137 in the direction of the arrow 170 across ametal-to n-type semiconductor junction 171 located between the firstmetal layer 127 and the n-type semiconductor material 128. Current flowthrough the metal-to n-type semiconductor results in thermal energybeing transmitted in the direction of arrow 172, opposite to thedirection of current flow. Thus, in this operational embodiment of FIG.1B, heat is drawn in the direction of junction 171 and away fromjunction 174. The resultant effect is that junction 171 is heated andjunction 174 is cooled. Consequently, thermal energy, or heat, is drawnto chip 125A and chip 125A is heated.

Conversely, if the layer 128 remains n-type but the current flow isreversed, e.g., the polarity of the voltage supply is reversed, thenthermal energy continues to be drawn opposite the direction of currentflow, but the direction is now in the direction of arrow 170. In thisoperational embodiment of FIG. 1B, heat is drawn away from first metallayer 127 with a resultant cooling effect at junction 171 and a heatingeffect at junction 174. In this embodiment, thermal energy, or Peltierheat is drawn away from chip 125A and chip 125A is cooled.

As is evident from the illustrations presented above, the choice ofsemiconductor type material, e.g. n or p-type, and the choice of currentdirection can be varied without departing from the scope of the presentinvention. And, these above stated variables can thus be coordinated toachieve a desired objective of either heating or cooling chip 125A.

In one embodiment, shown in FIG. 1B, an insulator layer 126 separatesthe first metal layer 127 from the semiconductor chip 125A. In oneembodiment, the adhesive insulator layer 126 includes any suitableepoxy. In an alternative embodiment, the insulator layer 126 can includeany suitable material, as the same will be understood upon reading thisdisclosure by one of ordinary skill in the art of semiconductorfabrication. In one embodiment, the first and second metal layers, 127and 129 respectively, are formed of copper (Cu). In an alternateembodiment, first and second metal layers, 127 and 129, are formed fromany suitable metal conductor as will by understood upon reading thisdisclosure by one of ordinary skill in the art of semiconductorfabrication.

FIG. 2 is a cross-sectional view illustrating another embodiment of aPeltier element 200 according to the teachings of the present invention.In FIG. 2, the direction in which the current, indicated by arrows 219,is passed through the n-type, 202A, 202B, . . . , 202C, etc. and thep-type, 203A, 203B, . . . , 203C, etc. semiconductor blocks determineswhich direction heat energy is transferred. The direction in which theheat energy, or Peltier heat, is transferred determines which surfaces201A, 201B, . . . , 201C, etc. or surfaces 204A, 204B, . . . , 204C,etc. are cooled and heated respectively. In example, with the currentpassing in the direction of arrows 219, heat is drawn in the directionof the current for current passing through a p-type semiconductormaterial, 203A, 203B, . . . , 203C, etc. and heat is drawn opposite tothe direction of current for current passing through an n-typesemiconductor material, 202A, 202B, . . . , 202C, etc. Thus, in theembodiment of FIG. 2, surfaces 201A, 201B, . . . , 201C, etc. areheated, and surfaces 204A, 204B, . . . , 204C, etc. are cooled.Conversely, if the current is reversed from the direction of arrows 219,then surfaces 201A, 201B, . . . , 201C, etc. are cooled, and surfaces204A, 204B, . . . , 204C, etc. are heated.

In addition to the semiconductor materials presented earlier, Peltierelements can be formed from a range of other metal-to-metal, ormetal-to-semiconductor combinations. FIG. 2 aids in illustratingalternative embodiments of a Peltier element constructed from such othercombinations. As will be understood by one of ordinary skill in the artof semiconductor fabrication from reading this disclosure, substitutionof these other combinations is included within the scope of the presentinvention. The following alternative embodiments provide example of thisand all offer a high coefficient of performance (COP). In one exemplaryembodiment each of the following combinations is adapted to provide aCOP of at least 0.6 or better.

In FIG. 2 an embodiment of an isolated illustration of a Peltier element200 is provided. In one embodiment, Peltier element 200 includesinterfaces, or junctions, of metal-to-metal, or metal-to-semiconductormaterials. In the exemplary embodiment, the Peltier element 200 of FIG.2 can be suitably fabricated upon a semiconductor wafer. In oneexemplary alternative embodiment, the n-type layers, or blocks, 202A,202B, . . . , 202C, etc. and the p-type layers, or blocks, 203A, 203B, .. . , 203C, etc. include appropriately doped complex oxidesemiconductors. In one embodiment, the complex oxide semiconductorsinclude strontium (Sr) and titanium (Ti). In this embodiment the complexoxide semiconductors possess an oxygen deficiency.

The following materials are also well suited for inclusion as the n-typesemiconductor layers, or blocks, 202A, 202B, . . . , 202C, etc. and thep-type semiconductor layers, or blocks, 203A, 203B, . . . , 203C, etc.In one embodiment, the n-type semiconductor layers, or blocks, 202A,202B, . . . , 202C, etc. and the p-type semiconductor layers, or blocks,203A, 203B, . . . , 203C, etc. are formed from a superlattice comprisingalternating layers of (PbTeSe)_(m) and (BiSb)_(n) where m and n are thenumber of PbTeSe and BiSb monolayers per superlattice period. In anotherembodiment, the n-type semiconductor layers, or blocks, 202A, 202B, . .. , 202C, etc. and the p-type semiconductor layers, or blocks, 203A,203B, . . . , 203C, etc. include semiconductor alloys formed betweenAntimony (Sb) and a transition metal (T) of Group VIII, includingCobalt, Rhodium, and Iridium (Co, Rh, and Ir), and wherein the alloy hasthe general formula Tsb₃. In this embodiment, the semiconductor alloyincludes a skutterudite-type crystal lattice.

Similarly well suited to the teachings of the present invention arePeltier elements 200 fabricated by thin film technology onto thebackside of an semiconductor chip. An optimization of Bi₂Te₃ filmsincludes forming a Copper (Cu) and doped Bismuth Telluride (Bi₂Te₃)junction using vacuum evaporation to form a thin film of p or n-dopedBismuth Telluride (Bi₂Te₃). An alternate thin film junction is formedusing vacuum evaporation to form a thin film of p or n-doped AntimonyTelluride (Sb₂Te₃). The method for such an embodiments, is provided, forexample, according to the methods taught by C. Shafai and M.J. Brett,“Optimization of Bi₂Te₃ thin films for microintegrated Peltier heatpumps”, Journal of Vacuum Science and Technology A, vol.15, no. 5, p.2798-801, 1997, and C. Shafai and M.J. Brett, “A micro-integratedPeltier heat pump for localized on-chip temperature control”, CanadianJournal of Physics, vol. 74, no. 1, p. S139-42, 1996.

One of ordinary skill in the art of semiconductor fabrication will, uponreading this disclosure, understand the manner in which to construct thesame. As explained above in detail relative to FIGS. 1B and 2, dopingand current flow direction determine the direction in which thermalenergy will be transported in these various alternative embodiments. Thedoping and current flow direction are arranged in accordance to thePeltier effect physical laws to either draw Peltier heat to or away froma chosen component. The effect being that the selected component iseither cooled or heated as desired.

FIG. 3 is a block diagram illustrating an electronic system 300according to an embodiment of the present invention. The electronicsystem 300 includes an electronic packaging assembly 305. The electronicpackaging system 305 includes the electronic packaging assembly 305presented and described in detail above. The electronic packagingassembly 305, specifically includes a semiconductor chip which isfurther coupled to a metal-to-semiconductor junction. The electronicsystem 300 includes a number of external devices 310. The number ofexternal devices 310 include, for example, memory controllers,microprocessors and input/output bus units. The electronic system 300includes a system bus 320. The system bus 320 couples the number ofexternal devices 310 to the electronic packaging assembly 305.

FIGS. 4A-4G illustrate an embodiment of the various processing steps forfabricating the number of electrical connections 135 through the siliconinterposer 110, as illustrated in FIG. 1. FIGS. 4A-4G illustrate anembodiment for forming salicided connections 135 through the siliconinterposer 110. FIG. 4A, is a top view illustrating generally asemiconductor wafer fragment at 10.

In FIG. 4B, a cross-sectional view of FIG. 4A, taken along cut-lines4B-4B, is provided. The semiconductor wafer fragment at 10 includes asemiconductor conductive substrate. Wafer fragment 10 includes a frontsurface 14 and a back surface 16 and a thickness (t) which is definedbetween the surfaces. An exemplary thickness is around 30 mils orbetween around 750 to 800 micrometers (μm). FIG. 4B illustrates thatamounts of the semiconductor conductive wafer material are removed toform holes or passageways 18, 20, and 22. In one embodiment, such holesare formed to a depth of not less than half of thickness (t). In oneexemplary embodiment, holes 18, 20 and 22 extend perpendicularly throughthe entirety of wafer fragment 12 and join with front and back surfaces14 and 16, respectively. In the exemplary embodiment, holes 18, 20, and22 have aspect ratios greater than about 50. In another exemplaryembodiment, the holes 18, 20, and 22 have aspect ratios between about 75and 80.

In a preferred implementation, holes 18, 20, and 22 are formed orotherwise provided prior to processing of any integrated circuitrydevices over either of surfaces 14, 16. In other words, the holes areformed prior to patterning any conductive material which is associatedwith integrated circuitry devices to be formed over either of surfaces14 and 16. The holes 18, 20, and 22 are formed through suitable etchingtechniques. Alternatively, such holes are formed or drilled with asuitable laser. In one exemplary embodiment, very high aspect ratioholes are formed by placing the wafer in a semiconductor wafer processorincluding a dipole-ring magnetron etching reactor after which, the waferis exposed to conditions within the dipole ring magnetron etchingreactor which are sufficient to form holes which extend through theentirety of the wafer. A suitable dipole ring magnetron (DRM) reactor isdescribed in an article entitled “Trench Storage Node Technology forGigabit DRAM Generations,” Technical Digest of International ElectronDevices Meeting, Dec. 8-11, 1996, pages 507-510, published IEEE, CatalogNo. 96CH35961 and authored by Muller et al. Likewise, a suitable DRMsystem and exemplary processing conditions are described in an articleentitled “A New High-Density Plasma Etching System Using a Dipole-RingMagnet,” Jpn. J. Appl. Phys., 34, pt. 1, no. 11, Nov. 1995, pages6274-6278, and authored by Sekine et al. After formation of the holes18, 20, and 22, the same can be temporarily filled with any materialsuch as a photoresist to enable subsequent processing of integratedcircuitry devices over either or both of surfaces 14 and 16.

As shown in FIG. 4C and in accordance with an exemplary embodiment,integrated circuitry is formed or otherwise processed and supported bywafer fragment 10. Integrated circuitry 24 can be formed over orproximate front surface 14, back surface 16, or both front and backsurfaces 14, 16, respectively.

In FIG. 4D, wafer fragment 10 is exposed to conditions which areeffective to form respective dielectric layers 28, 30, and 32 withineach of the holes 18, 20, and 22, and proximate the respective interiorsurfaces 19, 21 and 23 thereof. In one embodiment, dielectric layers 28,30, and 32 comprise a nitride-containing layer which is disposedproximate respective interior surfaces 19, 21, and 23. Anoxide-containing layer is formed over the nitride-containing layer toprovide a dielectric (NO) layer within the hole. In an exemplaryembodiment, a nitride-containing layer is formed through chemical vapordeposition (CVD) and the oxide layer by exposing the substrate tooxidizing conditions. In one exemplary embodiment, dielectric layers 28,30 and 32 can constitute reoxidized, low-pressure, chemical vapordeposition (LPCVD) on nitride film which forms the illustrated andpreferred (NO) dielectric layer. An exemplary processing implementationincludes in situ nitridation in ammonia an 950° C. LPCVD of nitride at700° C. takes place with dichlorosilane and ammonia. Subsequently,reoxidation of the nitride takes place at a temperature between 900° C.and 950° C. Alternatively, fast thermal processing (FTP) can implementthe above-described three processing steps into a single processing run.Exemplary processing methods and systems are described in the Mueller etal. article referenced above. Alternatively, dielectric layers 28, 30and 32 can comprise a thin, silicon dioxide film. A desired andexemplary thickness of such layers is between 50-100 nanometers (nm).

In FIG. 4E, electrical interconnect material 34, 36 and 38 is formedwithin holes 18, 20 and 22 respectively. Such material fills each holeand is capable of electrically interconnecting integrated circuitryformed over both front and back surfaces 14 and 16 respectively. In apreferred implementation, interconnect material 34, 36 and 38 constitutea first material which is formed within each respective hole andcomprises polysilicon which is formed through CVD. Excess first materialcan be removed through conventional steps such as chemical mechanicalplanarization (CMP).

In FIG. 4F, a second layer of electrically conductive material 40 isformed over the first material 34, 36 and 38. In one embodiment, suchmaterial is formed over both front and back surfaces 14 and 16respectively. In another embodiment, second material 40 constitutescomprising a metal material which is different from first material 34and 36 and 38. In an exemplary embodiment, second material 40constitutes an aluminum comprising layer or film. Such material film canbe deposited through suitable sputtering or evaporation techniques.Mechanical mask can be utilized in order to define with moreparticularity the area over which the preferred aluminum layer isdeposited. Alternatively, such a layer can be blanket deposited andsubsequently processed as described below.

FIG. 4G illustrates the wafer fragment 10 is exposed to processingconditions which are effective to cause the second material 40 toreplace the first material 34, 36 and 38. In an exemplary embodiment,the first material 34, 36 and 38 is completely replaced with the secondmaterial 40 and the second material 40 electrically interconnects atleast some of the front surface integrated circuitry 24 with at leastsome back surface integrated circuitry 26. Exemplary processingconditions include annealing the wafer at a temperature greater than orequal to about 500° C. for a sufficient amount of time. The thickness ofthe second material 40 will be determined by the size and dimensions ofthe interconnecting holes or passageways. As a guideline, and for a0.175 micron diameter and 1.7 micron deep hole with an aspect ratio of10, an aluminum thickness of 0.5 micrometers (μm) is sufficient tosubstitute the preferred polysilicon. Annealing times and temperaturescan be decreased by forming a thin, e.g., 0.2 micrometer, titanium (Ti)layer over material 40 prior to annealing. The Ti layer acts as apolysilicon capture layer which accelerates the replacement ofpolysilicon with aluminum. Exemplary processing methods are described inan article entitled “Novel High-Aspect Ratio Plug for Logic/DRAM LSIsUsing Polysilicon-Aluminum Substrate (PAS),” Technical Digest ofInternational Electron Devices Meeting, Dec. 8-11, 1996, pages 946-948,published by IEEE, catalog number 96CH35961 and authored by Horie et al.Excess aluminum in the substitute for polysilicon can be removed throughsuitable processing techniques such as CMP. Alternately considered, aconductive interconnect is provided within wafer fragment 10 between andelectrically connecting at least a portion of the front-formedintegrated circuitry and the back-formed integrated circuitry. In theillustrated example, the integrated circuitry is formed in advance ofthe formation of the conductive interconnect.

In an alternate embodiment of the present invention, a method of formingcoaxial integrated circuitry and interconnect lines is provided inapplication Ser. No. 08/917,449 entitled, “Methods of Forming CoaxialIntegrated Circuitry Interconnect Lines, and Integrated Circuitry” filedon Aug. 22, 1997, which application is incorporated herein by reference.

FIG. 5 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention. A silicon interposer isformed at 510. The silicon interposer includes micro-machined viasformed through the silicon interposer. A number of flip chips areattached to the silicon interposer at 520. The flip chips couple to themicro-machined vias. A Peltier element is coupled to at least one of theflip chips at 530.

FIG. 6 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention. A silicon interposer isprovided at 610. The silicon interposer has opposing sides. Asemiconductor chip is coupled to each of the opposing sides of thesilicon interposer at 620. Next, the semiconductor chips on each side ofthe silicon interposer are coupled to one another by a number ofmicro-machined vias at 630. A Peltier element is coupled to at least oneof the semiconductors chips at 640.

FIG. 7 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention. A silicon interposer isprovided at 710. The silicon interposer has opposing sides. Asemiconductor chip is coupled to each of the opposing sides of thesilicon interposer at 720. Next, the semiconductor chips on each side ofthe silicon interposer are coupled to one another by a number ofmicro-machined vias at 730. The micro-machined vias provided electricalconnections between the opposing sides of the silicon interposer. Ametal-to-semiconductor junction is coupled to at least one of thesemiconductor chips at 740.

FIG. 8 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention. A silicon interposer isprovided at 810. The silicon interposer has opposing sides. A firstsemiconductor chip is coupled to a first side of the silicon interposerat 820. Next, a second semiconductor chip is coupled to a second side ofthe silicon interposer at 830. A metal-to-semiconductor junction isformed which couples to the first semiconductor chip at 840. At 850, acurrent is passed through the metal-to-semiconductor junction in adirection such that a Peltier cooling effect occurs adjacent to thefirst semiconductor chip.

FIG. 9 illustrates, in flow diagram form, a methodical aspect accordingto the teachings of the present invention. A silicon interposer isprovided at 910. The silicon interposer has opposing sides. A firstsemiconductor chip is coupled to a first side of the silicon interposerat 920. Next, a second semiconductor chip is coupled to a second side ofthe silicon interposer at 930. A metal-to-semiconductor junction isformed which couples to the first semiconductor chip at 940. At 950, acurrent is passed through the metal-to-semiconductor junction in adirection such that a Peltier heating effect occurs adjacent to thefirst semiconductor chip.

CONCLUSION

Thus, an improved integrated circuit package for providing built-inheating or cooling to a semiconductor chip is provided. The improvedintegrated circuit package provides increased operational bandwidthbetween different circuit devices, e.g. logic and memory chips. Theimproved integrated circuit package does not require changes in currentCMOS processing techniques. The structure includes the use of a siliconinterposer. The silicon interposer can consist of recycled rejectedwafers from the front-end semiconductor processing. Micro-machined viasare formed through the silicon interposer. The micro-machined viasinclude electrical contacts which couple various integrated circuitdevices located on the opposing surfaces of the silicon interposer. Thepackaging includes a Peltier element.

The Peltier element, using semiconductor-based materials, functions as asmall heat pump. By applying a low-voltage d-c current to the Peltierelement thermal energy is transferred with the effect that one portionof the Peltier element is cooled and another heated. In one embodiment,the heated portion of the Peltier element is in contact with a heat sinkor the outer cover of the integrated circuit package and the cooledportion is in contact with a semiconductor chip. In an alternativeembodiment, the arrangement is reversed. This design has no movingparts, is small in size and lightweight, and has the ability to coolbelow or heat above the ambient temperature surrounding integratedcircuit devices.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A method for packaging an integrated circuit, comprising: providing asilicon interposer having opposing sides; coupling a semiconductor chipto each of the opposing sides of the silicon interposer; coupling thesemiconductor chips on each side of the silicon interposer to oneanother through the silicon interposer by a number of micro-machinedvias, wherein the micro-machined vias provide electrical connectionsbetween the opposing sides of the silicon interposer; coupling ametal-to-semiconductor junction to at least one of the semiconductorchips, wherein the semiconductor includes a doped complex oxidesemiconductor.
 2. The method of claim 1, wherein coupling a dopedcomplex oxide semiconductor includes coupling an n-doped complex oxidesemiconductor comprising Strontium (Sr) and Titanium (Ti).
 3. The methodof claim 1, wherein coupling a doped complex oxide semiconductorincludes coupling an oxygen deficient an n-doped complex oxidesemiconductor.
 4. The method of claim 1, wherein the semiconductor chipsinclude a flip chip.
 5. The method of claim 4, wherein a Peltier elementis coupled to a flip chip.
 6. The method of claim 1, wherein thesemiconductor chips includes a memory chip.
 7. The method of claim 6,wherein the memory chip includes at least one of a dynamic random accessmemory (DRAM) chip, a flash memory chip and a static random accessmemory (SRAM) chip.
 8. The method of claim 6, wherein the semiconductorchips include capacitors.
 9. A method for packaging an integratedcircuit, comprising: providing a silicon interposer having opposingsides; coupling a semiconductor chip to each of the opposing sides ofthe silicon interposer; coupling the semiconductor chips on each side ofthe silicon interposer to one another through the silicon interposer bya number of micro-machined vias, wherein the micro-machined vias provideelectrical connections between the opposing sides of the siliconinterposer; coupling a metal-to-semiconductor junction to at least oneof the semiconductor chips, wherein the semiconductor includes ann-doped superlattice comprising alternating layers of (PbTeSe)m and(BiSb)n, where m and n are the number of PbTeSe and BiSb monolayers persuperlattice period.
 10. The method of claim 9, wherein thesemiconductor chips include a flip chip.
 11. The method of claim 10,wherein a Peltier element is coupled to a flip chip.
 12. The method ofclaim 9, wherein the semiconductor chips includes a memory chip.
 13. Themethod of claim 12, wherein the memory chip includes at least one of adynamic random access memory (DRAM) chip, a flash memory chip and astatic random access memory (SRAM) chip.
 14. The method of claim 12,wherein the semiconductor chips include capacitors.
 15. A method forpackaging an integrated circuit, comprising: providing a siliconinterposer having opposing sides; coupling a semiconductor chip to eachof the opposing sides of the silicon interposer; coupling thesemiconductor chips on each side of the silicon interposer to oneanother through the silicon interposer by a number of micro-machinedvias, wherein the micro-machined vias provide electrical connectionsbetween the opposing sides of the silicon interposer; coupling ametal-to-semiconductor junction to at least one of the semiconductorchips, wherein the semiconductor includes either an n or p-dopedsemiconductor alloy formed between Antimony (Sb) and transition metal(T) from Group VIII, including Cobalt (Co), Rhodium (Rh), and Iridium(Ir), and wherein the alloy has the general formula TSb3.
 16. The methodof claim 15, wherein the semiconductor chips include a flip chip. 17.The method of claim 16, wherein a Peltier element is coupled to a flipchip.
 18. The method of claim 15, wherein the semiconductor chipsincludes a memory chip.
 19. The method of claim 16, wherein the memorychip includes at least one of a dynamic random access memory (DRAM)chip, a flash memory chip and a static random access memory (SRAM) chip.20. The method of claim 16, wherein the semiconductor chips includecapacitors.
 21. A method for cooling an integrated circuit, comprising:providing a silicon interposer having opposing sides; coupling a firstsemiconductor chip to a first side of the silicon interposer; coupling asecond semiconductor chip to a second side of the silicon interposer,wherein a number of electrical connections through the siliconinterposer couple the first semiconductor chip to the secondsemiconductor chip; forming a metal-to-semiconductor junction whichcouples to the first semiconductor chip on the first side of the siliconinterposer, wherein forming the metal-to-semiconductor junction includesforming a Copper (Cu) and n or p-doped semiconductor junction, whereinthe semiconductor is selected from Bismuth Telluride (Bi2Te3), LeadTelluride (PbTe), and Silicon Germanium (SiGe); and passing currentthrough the metal-to-semiconductor junction in a direction such that aPeltier cooling effect occurs adjacent to the first semiconductor chip.22. The method of claim 21, wherein the semiconductor chips include aflip chip.
 23. The method of claim 22, wherein a Peltier element iscoupled to a flip chip.
 24. The method of claim 21, wherein thesemiconductor chips includes a memory chip.
 25. The method of claim 24,wherein the memory chip includes at least one of a dynamic random accessmemory (DRAM) chip, a flash memory chip and a static random accessmemory (SRAM) chip.
 26. The method of claim 21, wherein thesemiconductor chips include capacitors.
 27. A method for cooling anintegrated circuit, comprising: providing a silicon interposer havingopposing sides; coupling a first plurality of semiconductor chips to afirst side of the silicon interposer; coupling at least one Peltierelement to one of the first side of the silicon interposer and on of thefirst plurality of semiconductor chips; and coupling a second pluralityof semiconductor chips to a second side of the silicon interposerwherein a number of electrical connections through the siliconinterposer couple the first plurality of semiconductor chips to thesecond plurality of semiconductor chips.
 28. The method of claim 27,wherein the first plurality of semiconductor chips includes flip chips,and the at least one Peltier element is coupled to a selected one of theflip chips.
 29. The method of claim 27, wherein the second plurality ofsemiconductor chips includes a memory chip.
 30. The method of claim 29,wherein the memory chip includes at least one of a dynamic random accessmemory (DRAM) chip, a flash memory chip and a static random accessmemory (SRAM) chip.
 31. The method of claim 29, wherein the secondplurality includes semiconductor chip capacitors.